ICFPT 2014

ICFPT 2014 Design Contest: Blokus Duo

News

December 26: The result and logs of Design Competition has been updated.
December 25: Honors and awards of Design Competition has been updated.
November 15: The Schedule of Design Competition has been updated.
August 20: The Submission Guidelines of Design Competition Paper have been updated.
May 26: Altera and Xilinx will provide boards for the winners, based on the FPGA devices they use for the competition.
May 26: The reference link HEART2014.
May 26: The Design Competition Website has been updated.

Schedule

Pre-competition check: Dec.09 13:00-14:00
Pre-Finals: Dec.09 14:00-17:00
Finals: Dec.10 17:00-18:00

Honors and Awards

Rank	Team Name	Affiliation	Member
1st	University of Zaragoza	University of Zaragoza	Javier Olivito, Alberto Delmás and Javier Resano
2nd	Shizuoka FPGA Blokus Duo Solver II			Shizuoka University	Takumi Fujimori, Retsu Moriwaki, Masato Seo, Kouta Akagi, Hiroyuki Ito, Takayuki Kubota, Shinya Furukawa, and Minoru Watanabe
2nd	Kuma2Duo	Kumamoto University	Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi
3rd	SAKURA-Duo			Nagasaki University	Rie Soejima, Kota Aoki, Kaoru Hamasaki, Masahito Oishi, Koji Okina, Jimpei Hamamura, Shun Kashiwagi, Yoshiki Hayashida, Ryo Fujita, Yudai Shirakura, Fumihiko Iwasaki, Tai Noguchi, Aiko Iwasaki, Kota Fukumoto and Yuichiro Shibata
3rd	Shizuoka FPGA Blokus Duo Solver I	Shizuoka University	Takumi Fujimori, Retsu Moriwaki, Masato Seo, Kouta Akagi, Hiroyuki Ito, Takayuki Kubota, Shinya Furukawa, and Minoru Watanabe
3rd	HLAB			Keio University	Naru Sugimoto and Hideharu Amano
3rd	BLUE STORM	Ritsumeikan University	Masashi Ohno, Yuu Nakahara, Kazuya Ohtsu, Tatsuya Suzuki, Tomonori Izumi and Meng Lin
Participation Award	UT_PatOMat			University of Tehran	Ehsan Qasemi, Amir Samadi, Mohammad H. Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian and Bijan Alizadeh
Participation Award	ERTL	Nagoya University	Masataka Ogawa, Yuki Ando, Shinya Honda, Go Sato and Yusuke Kato
Participation Award	Reconfigurable Application Diffusion Committee			Hiroshima City University	Akira Kojima
Participation Award	PARMA	Islamic Azad University	Hossein Borhanifar and Seyed Peyman Zolnouri

The Competitors

Paper ID	Team ID	Paper Name	Team Name	Affiliation	Member
116	BD	An FPGA Blokus Duo Solver with a high activity	Shizuoka FPGA Blokus Duo Solver I	Shizuoka University	Takumi Fujimori, Retsu Moriwaki, Masato Seo, Kouta Akagi, Hiroyuki Ito, Takayuki Kubota, Shinya Furukawa, and Minoru Watanabe
117	BE					Stratics FPGA Blokus Duo Solver	Shizuoka FPGA Blokus Duo Solver II	Shizuoka University	Takumi Fujimori, Retsu Moriwaki, Masato Seo, Kouta Akagi, Hiroyuki Ito, Takayuki Kubota, Shinya Furukawa, and Minoru Watanabe
118	PH	An improved FPGA Blokus player via Alpha-Betha pruning and Monte-Carlo algorithm	Pure Hardware	Institute for Research in Fundamental Science (IPM)	Nariman Eskandari, Ali Jahanshahi and Mohammad Kazem Taram
119	SD					The stochastic Blokus Duo Solver	SAKURA-Duo	Nagasaki University	Rie Soejima, Kota Aoki, Kaoru Hamasaki, Masahito Oishi, Koji Okina, Jimpei Hamamura, Shun Kashiwagi, Yoshiki Hayashida, Ryo Fujita, Yudai Shirakura, Fumihiko Iwasaki, Tai Noguchi, Aiko Iwasaki, Kota Fukumoto and Yuichiro Shibata
120	KU	Blokus Duo Engine on a Zynq	Kuma2Duo	Kumamoto University	Susumu Mashimo and Kansuke Fukuda
122	UT					HW/SW Co-Design of Highly Scalable, SharedMemory , Monte-Carlo Tree Search based Blokus Duo Solver on FPGA	UT_PatOMat	University of Tehran	Ehsan Qasemi, Amir Samadi, Mohammad Hadi Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian and Bijan Alizadeh
123	UZ	An improved FPGA-based specific processor for Blokus Duo	University of Zaragoza	University of Zaragoza	Javier Olivito, Alberto Delmás and Javier Resano
124	ER					Developing an FPGA Blokus Duo Solver By System-Level Design	ERTL	Nagoya University	Masataka Ogawa, Yuki Ando, Shinya Honda, Go Sato and Yusuke Kato
125	RA	FPGA Implementation of Blokus Duo Player using Hardware/Software Co-Design	Reconfigurable Application Diffusion Committee	Hiroshima City University	Akira Kojima
126	HF					Hardware/Software co-design Architecture for Blokus Duo Solver	HLAB	Keio University	Naru Sugimoto and Hideharu Amano
127	PA	Optimize MinMax Algorithm to solve Blokus Due Game by HDL	PARMA	Islamic Azad University, Nazar Abad Center	Hossein Borhanifar and Seyed Peyman Zolnouri
128	TJ					Blokus Duo Player Based on ZYBO	TJUplayer	Tianjin University	Song Xu and Lin Wang
149	RB	BLUE STORM - BLokus Unified Engine of Search and Test Operation by RitsuMei	BLUE STORM	Ritsumeikan University	Masashi Ohno, Yuu Nakahara, Kazuya Ohtsu, Tatsuya Suzuki, Tomonori Izumi and Meng Lin
150	TO					An Implementation of Multi Game AI System of Blokus Duo on FPGA with NSL	ToK-AI	Tokai University	Ryo Tamaki

Introduction

Following the successful FPGA design competition in ICFPT 2013, we're planning another Blokus Duo design contest in ICFPT 2014. It'll be basically same to the ICFPT 2013 design competition, but we expect several changes in the regulation, along the scope of HEART symposium and ICFPT 2014.

Blokus Duo is a two-player game played on a square, 14x14 grid board. Each player has 21 different-shaped game tiles. Each new piece played must be placed to contact at least one piece of the same color with their corner-to-corner. Edge-to-edge contact is only allowed to the other color.

FPGA contest

In ICFPT 2014, we'll have a design contest on Blokus Duo. Only the FPGA-to-FPGA matches are allowed in ICFPT 2014.

FPGA category

Same as traditional FPGA design contest in HEART 2012, ICFPT 2013 or HEART 2014.
See the approved FPGA board / device list in the "Tools" page.

Every contest design (boards or computers) must be on site and connected to the host PC via RS-232C. The pre-finals will be competed within each category, then the best designs will go to the final exhibition matches.

Important Dates

Entry of design competition: Sep. 9, 2014
Submission of design competition papers: Oct. 1, 2014
Notification: Oct. 10, 2014
Final Version Submission: Oct. 31, 2014

Submission Guidelines

1. By 9 September, submit an abstract through Softconf, including title, team members and affiliation, design description such as:

- Device / Board

- HSL / HDL

- Design Tool (Altera Quartus II, Xilinx ISE, Impulse C, etc.)

- Strategy (Alpha-Beta, Min-max, etc.) and so on.

2. By 1 October, submit a 4-page design competition paper or just an abstract following the FPT paper template through Softconf. The 4-page paper should include detailed description about the design and performance evaluation. The selected design competition papers will be published in the proceedings. If only abstract is submitted, then the abstract will not be published in the proceedings. All teams are welcome to attend the competition, disregarding the design competition paper acceptance.