Programmable Multimedia Platform

based on Samsung Reconfigurable Processor

                                                                                        by Sukjin Kim, Samsung

 

Abstract

In this talk, we introduce the programmable multimedia platform based on Samsung’s proprietary DSP, named Samsung Reconfigurable Processor (SRP). SRP has been widely used in Samsung’s products from camera, digital TV to smartphone already, and even widening its usage to the next generation UHD TV and printer. In order to support massive computation and memory bandwidth of ever-demanding target applications, the SRP based platform implemented several key features such as symmetric multi-cluster architecture for data partitioning, ring data-path between clusters for supporting data pipelining, and hybrid architecture of hardware accelerators with SRP for computing enhancement of well-defined algorithms.

 

In addition, under the circumstances of continuously evolving and changing algorithms for products (such as post video processing for UHD TV), flexibility of the system is crucial to support new algorithm and thus retain competitiveness. Programmability and reconfigurability of SRP as main core of the platform makes it possible to upgrade the algorithm even after a chip has been fabricated. The proposed system will be used for the upcoming Samsung 8K UHD TV.

 

 

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Staying a Generation Ahead

                                                                                        by Jason Wong, Xilinx

 

Abstract

Xilinx has developed even more advanced FPGAs, the second generation SoCs and 3D ICs to stay a generation ahead, and deliver an extra node worth of performance, power, and integration. The UltraScale architecture was developed to scale from 20nm planar through 16nm and beyond FinFET (FF) technologies, and from monolithic through 3D ICs.

 

In this talk, we will study the cases about Xilinx FPGAs in cutting edge applications, and the advantages of UltraScale architecture, the second generation SoCs and design tools.

 

 

 

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IoT and Wearable Applications Enabled

by Bluetooth Low Energy (BLE) Solutions

                                                                                        by Patrick Kane, Cypress

 

Abstract

The Internet of things is happening right now. The newest standard is Bluetooth Low Energy or BLE. This may or may not be the long term answer to IoT communication, but it is certainly in the race to become the leading IoT communication standard.

 

 

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The Implementation Methodology of FPGA in Future

                                                                                        by Dylan Wang, Altera

 

Abstract

In this talk, we will show how to use DSP builder, OpenCL and QSys tools to design a system easily in future by building the frame work with the kernel processing IPs without even know anything about FPGA.

 

DSP builder

DSP Builder advanced blockset consists of several Simulink libraries that allow you to implement DSP designs quickly and easily. DSP Builder is a high-level synthesis technology that optimizes the high-level, untimed netlist into low level, pipelined hardware for your target Altera FPGA device and desired clock rate. DSP Builder implements the hardware as VHDL with scripts that integrate with the Quartus II software and the ModelSim simulator.

You can create designs without needing detailed device knowledge and generate designs that run on a variety of FPGA families with different hardware architectures.

DSP Builder allows you to manually describe algorithmic functions and apply rule-based methods to generate hardware optimized code. The advanced blockset is particularly suited for streaming algorithms characterized by continuous data streams and occasional control. For example, RF card designs that comprise long filter chains.

 

OpenCL

The Altera(r) SDK for Open Computing Language (OpenCLTM) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, or prototype the accelerator kernel on a virtual FPGA fabric in minutes, pushing the longer compile time to the end when you are pleased with your kernel code results.

 

QSys

Qsys is a system integration tool included as part of the Quartus(r) II software. Qsys captures system-level hardware designs at a high level of abstraction and automates the task of defining and integrating customized HDL components, which may include IP cores, verification IP, and other design modules. Qsys facilitates design reuse by packaging and making available your custom components and systems, and integrates your custom components with Altera(r) and third-party developer components.

Qsys automatically creates interconnect logic from the connectivity options you specify, eliminating the error-prone and time-consuming task of writing HDL to specify the system-level connections.

Qsys uses standard Avalon(r), AMBA(r) AXI3(tm) (version 1.0) and AMBA AXI4(tm) (version 2.0) interfaces that you can use to create your custom IP components. Connections between Avalon and AXI interfaces are allowed and can be achieved without requiring the use of bridges; Qsys interconnect provides the necessary bridging logic. To present the idea how we can use the advanced tools to build a system easily in future.

 

 

 

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On-Chip Loop Timing Design on a Virtex-7 FPGA

                                                                                        by Bo He, ZTE

 

Abstract

In the application of wireline and wireless systems, the interfaces are required to have their transmitters follow the frequencies of the receivers, which is called loop timing, like SDH, SONET, and SDI interfaces. In the previous design solutions, it's usually realized by adding external PLL chipsets. However, Virtex-7 series with phase interpolator (PI) module and logical digital filter implemented by logic, the loop timing is flexibly achieved with no need of external PLL chipsets. In this talk, we will briefly introduce the loop timing feature of SDH/SONET interface realized on PI module in Virtex-7 platform, as well as the test of the output jitter.

 

 

 

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China Programmable IC: Innovation with CAP Technology

                                                                                        by Dr. Ming Liu, Capital Microelectronics

 

Abstract

Being the only vendor of programmable IC products outside of United States, Capital Microelectronics (CME), located in Beijing, has independently developed its intellectual property and successfully delivered programmable SOC products integrating FPGA, CPU, ADC, ASIC, SRAM and Flash since 2005. CME has applied for 165 patents, with 88 have been granted. The company's innovating Configurable Application Platform (CAP) offers ability to reconfiguration along with highly demanded IPs, integrated design environment and software tools which are easy to use, flexible and cost effective solution for system integrators and application developers. Since 2011, the company has announced a few low cost chips of its “Mountain” family devices (CME-M) and a couple of ultra-low power chips of its “River” family devices (CME-R), which have been configured into hundreds of products to provide a variety of flexible solutions for customers to choose. These chips scale up to millions of gates to meet a wide range of low to middle end market demands. Meanwhile, the company is developing high-density and high performance “Cloud” family devices (CME-C).

 

Because of continuous market segmentation and evolution, traditional ASICs, even with high efficiency and low cost for certain fixed market segments, are now facing more and more challenges and risks in ROI, due to sharp rise in R&D and manufacturing cost. On the other hand, the performance/price ratio of FPGA products has been greatly improving along with semiconductor process node advancement. Since a single FPGA chip can meet a variety of market demands in different industries and areas, and its competitive advantage in time to market and adaptability to market change, FPGA has become a new development trend in IC industry.

 

Given its flexibility and adaptability in “custom made and mass produced”, the multi-function and high performance and low cost CAP developed and commercialized by CME has greatly broaden its application coverage, and become a key device in “China Intelligent Manufacture”. CME-M family products have been applied to traditional FPGA markets, e.g. video display, industrial control, information security, telecom equipment, monitor and surveillance, medical instruments, automobile electronics, network switching, consumer appliances……whereas CME-R family products has gradually found their way in new market areas such as intelligent mobile phones, IOT devices, wearable products due to their competitive advantages in ultra-low power and high performance/price ratio. Compare to traditional FPGA chips, stand-alone CPU chips, or ASIC/ASSP chips, CME products have the following competitive advantages: (1) high reliability; (2) low BOM cost; (3) long product life cycle; (4) great system performance; (5) fast application development. This type of system products with “programmable software and reconfigurable hardware” on the same chip will dominant market in the near future.